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Qué (quién) es XOP instruction set - definición
XOP instruction set
COMPUTER INSTRUCTION SET INTRODUCED BY AMD IN 2009
The XOP (eXtended Operations) instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the x86 and AMD64 instruction set for the Bulldozer processor core, which was released on October 12, 2011. However AMD removed support for XOP from Zen (microarchitecture) onward.
Reduced Instruction Set Computer
![An IBM [[PowerPC 601]] RISC microprocessor](https://commons.wikimedia.org/wiki/Special:FilePath/IBM PowerPC601 PPC601FD-080-2 top.jpg?width=200 "An IBM [[PowerPC 601]] RISC microprocessor")
PROCESSOR EXECUTING ONE INSTRUCTION IN MINIMAL CLOCK CYCLES
Reduced Instruction Set Computer; RISC processor; Reduced Instruction Set Code; Reduced Instruction Set Computing; RISC; RISC-based; RISC-based system; RISC System/6000 SP; Reduced instruction set; RISC architectures; RISC instruction set; RISC-based computer design approach; RISC principles; Reduced instruction set computing
<processor> (RISC) A processor whose design is based on the
rapid execution of a sequence of simple instructions rather
than on the provision of a large variety of complex
instructions (as in a Complex Instruction Set Computer).
Features which are generally found in RISC designs are uniform
instruction encoding (e.g. the op-code is always in the same
bit positions in each instruction which is always one word
long), which allows faster decoding; a homogenous {register
set}, allowing any register to be used in any context and
simplifying compiler design; and simple addressing modes
with more complex modes replaced by sequences of simple
arithmetic instructions.
Examples of (more or less) RISC processors are the {Berkeley
RISC}, HP-PA, Clipper, i960, AMD 29000, MIPS R2000
and DEC Alpha. IBM's first RISC computer was the RT/PC
(IBM 801), they now produce the RISC-based {RISC
System/6000} and SP/2 lines.
Despite Apple Computer's bogus claims for their
PowerPC-based Macintoshes, the first RISC processor used
in a personal computer was the Advanced RISC Machine (ARM)
used in the Acorn Archimedes.
(1997-06-03)
Reduced instruction set computer
PROCESSOR EXECUTING ONE INSTRUCTION IN MINIMAL CLOCK CYCLES
Reduced Instruction Set Computer; RISC processor; Reduced Instruction Set Code; Reduced Instruction Set Computing; RISC; RISC-based; RISC-based system; RISC System/6000 SP; Reduced instruction set; RISC architectures; RISC instruction set; RISC-based computer design approach; RISC principles; Reduced instruction set computing
In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set computer (CISC), a RISC computer might require more instructions (more code) in order to accomplish a task because the individual instructions are written in simpler code.
